Memory devices are widely used in electronic devices for storing data. Typically, such memory devices may be divided into at least two categories, dynamic random access memory (DRAM) and static random access memory (SRAM). DRAM generally has its data is periodically refreshed by rewriting the data to the memory to maintain the data. In contrast, SRAM typically does not require such a refresh. SRAM devices are widely used, for example, in cache memory of computers and portable appliances.
In general, memory cells of SRAM devices may be divided into two categories. One category includes memory cells employing load resistor as load devices of the memory cells. The other category is a CMOS type cell employing transistors as the load devices of the memory cells.
Memory devices using the CMOS type cell may be further divided into two types of cells. One is a thin film transistor (TFT) cell employing thin film transistors (TFTs) as the load devices, and the other is a full CMOS cell employing bulk transistors as the load devices. An equivalent circuit diagram of a general CMOS SRAM cell is illustrated in FIG. 1. Referring now to FIG. 1, the CMOS SRAM cell comprises a pair of driver transistors TD1 and TD2, a pair of transfer transistors TA1 and TA2, and a pair of load transistors TL1 and TL2. The pair of driver transistors TD1 and TD2 and the pair of transfer transistors TA1 and TA2 are NMOS transistors, while the pair of load transistors TL1 and TL2 are PMOS transistors.
The first driver transistor TD1 and the first transfer transistor TA1 are serially connected to each other. A source area of the first driver transistor TD1 is connected to a ground line Vss, and a drain area of the first transfer transistor TA1 is connected to a first bitline BL. Similarly, the second driver transistor TD2 and the second transfer transistor TA2 are serially connected to each other. A source area of the second driver transistor TD2 is connected to the ground line Vss, and a drain area of the second transfer transistor TA2 is connected to a second bitline /BL.
A source area and a drain area of the first load transistor TL1 are connected to a power line Vcc and a drain area of the first driver transistor TD1, respectively. Similarly, a source area and a drain area of the second load transistor TL2 are connected to the power line Vcc and a drain area of the second driver transistor TD2, respectively. A node N1 is defined at the drain region of the first load transistor TL1, the drain region of the first driver transistor TD1, and the source region of the first transfer transistor TA1. Also, a node N2 is defined at the drain region of the second load transistor TL2, the drain region of the second driver transistor TD2, and the source region of the second transfer transistor TA2. A gate electrode of the first driver transistor TD1 and a gate electrode of the first load transistor TL1 are connected to the second node N2. A gate electrode of the second driver transistor TD2 and a gate electrode of the second load transistor TL2 are connected to the first node N1. Gate electrodes of the first and second transfer transistors TA1 and TA2 are connected to a wordline WL.
The foregoing CMOS cell of FIG. 1 can exhibit a smaller stand-by current and a larger noise margin than the load resistor cell. The CMOS cell of FIG. 1 is widely used in a high-performance SRAM device, for example, in low power applications. The physical circuit corresponding to the CMOS SRAM cell shown in FIG. 1 can be constructed in various configurations at a semiconductor substrate. Conventionally, however, the full CMOS SRAM cell typically occupies a larger area than the corresponding load resistor cell or the thin film transistor (TFT) cell. Thus, improvements may be beneficial in the design of full CMOS SRAM cells.